1. Field of the Invention
The present invention relates to a method for fabricating vertical semiconductor devices, and in particular to a method of manufacturing heterojunction bipolar transistors using simplified processing, virtually eliminating the extrinsic parasitic base resistance and extrinsic parasitic base-collector and emitter-base capacitances and significantly reducing the base contact resistance.
2. Discussion of the Background
In manufacturing three-terminal vertical devices, such as a heterojunction bipolar transistor (HBT), collector, base and emitter layers are successively deposited on a substrate. Functionally, the contact to the base region is from the side but in practice it is made from the top of the device. The contact to the collector region is functionally from the bottom of the device but in practice it is also made from the top of the device in a region outside the area of the base contact. This results in an overlap of the base and collector extrinsic to the intrinsic device which results in an extrinsic parasitic base-collector capacitance. Furthermore, the top of the extrinsic base typically consists primarily of a metallized portion which determines the base contact resistance to the extrinsic base and a much smaller unmetallized portion which determines the extrinsic base resistance to the intrinsic device. Decreasing the overlap results in a reduction in extrinsic parasitic capacitance but generally increases the base contact resistance since less area is available for the base contact metal. Thus, the base contact resistance and extrinsic capacitance cannot in practice be simultaneously minimized. This reduces the optimum device performance which can be realized and necessitates a compromise between base contact resistance and extrinsic base-collector capacitance in order to achieve optimum device performance.
Various approaches have been made to reduce and/or eliminate this compromise between parasitic capacitance and resistance. For example, U.S. Pat. No. 4,939,562 to Alderstein discloses a method of manufacturing HBTs where the HBT structure is "grown" in reverse (emitter-down) configuration. Although this approach virtually eliminates the extrinsic base-collector capacitance, it does so by replacing the base contact resistance/extrinsic base-collector capacitance compromise with a base contact resistance/extrinsic base-emitter capacitance compromise and as such does not address the fundamental problem of overlap between emitter, base and/or collector layers extrinsic to the device which arises from performing all processing on the top side of the substrate.
Other methods have attempted to alleviate the extrinsic base contact resistance/extrinsic base-collector capacitance compromise by employing self-aligned features in the processing methods. In U.S. Pat. No. 4,824,805 to Kajikawa and U.S. Pat. No. 4,965,650 to Inada et al, emitter mesas are formed with photoresist layers disposed thereon having a predetermined overlap of the emitter mesa to provide self-aligned base contacts on either side of and close to the emitter mesa. Although these self-aligned techniques allow a net reduction in extrinsic parasitics compared to non-self-aligned techniques, they do not avoid the base contact resistance/extrinsic base-collector capacitance compromise described above.
A method for fabricating a compound semiconductor bipolar device is disclosed in U.S. Pat. No. 4,967,252 to Awano which reduces the extrinsic base-collector capacitance (in an emitter-up configuration) or the emitter-base capacitance (in an emitter-down configuration). This reduction is achieved by a combination of removing part of the collector from underneath the base in the extrinsic part of the device and reducing that part of the base extrinsic to the device by contacting the base from the side of the device. Removing part of the collector from underneath the base reduces the parasitic extrinsic base-collector capacitance by lowering the dielectric constant underneath that part of the base where the collector is removed; however, this capacitance is not eliminated because part of the collector remains underneath that part of the base extrinsic to the device. Moreover, contacting the base from the side of the device increases the base contact resistance for practical values of base sheet resistance (.rho..sub.s), contact resistivity (.rho..sub.c) and width (w) as follows. For a top base contact, the base resistance is given approximately as ##EQU1## where L.sub.t is the transfer length given as ##EQU2## and l.sub.c is the emitter length and S is the width of the base metal. This expression takes into account the resistance associated with the transition of a lateral current flow in the base semiconductor to a vertical flow into the base metal. For a side base contact, the lateral current flow in the base semiconductor remains lateral as it flows into the base metal. The base contact resistance for a side contact is thus given as ##EQU3## For practical values of base sheet resistance (&lt;420 ohms/square), contact resistivity (&gt;10.sup.-8 ohms-cm.sup.2) and width (&lt;10.sup.-5 cm), and assuming the base metal width for the top base contact is at least twice the transfer length, the contact resistance from side base contacts exceeds that from top base contacts since the ratio of top to side base contacts is given approximately by 2L.sub.t /w. Thus, the advantages of eliminating the extrinsic capacitance according to Awano are generally offset by an increased contact resistance.
Furthermore, the process according to Awano is somewhat complicated and entails a number of critical etching processes requiring careful monitoring and control. The resulting structure is very complicated and all processing is performed on the front side of the substrate.